richlowe: I think the state of the art involves monitoring perf counters to see if a thread might benefit from the big cores.

pack things into the efficient cores until they're full, and if they're 100% busy start picking threads to run on the performance cores.

would likely need some sort of fudge factors for FSS shares (X ticks on a P core is worth Y on an E?)

exactly which performance counters are meaningful for this likely depends on the specific pairing of core types..

Isn’t the feature set different? I though E-cores liked things like AVX, AES-NI,… ?

sjorge: in some cases, yes. (I think the AMD 4 vs 4c cores are same ABI but different cache sizes and different clock margins/turbo boost) if anything, that makes the question of who runs on the big cores easier.