01:06:10 <rmustacc> danmcd: No, you shouldn't have to introduct a new value per se. There isn't another save mechanism really.
01:06:30 <rmustacc> There are definitely challenges if you need amx, but we shouldn't be enabling that.
06:57:18 <danmcd> Oh I don't need amx, but for some reason, cpuid_get_xsave_size() is returning 0x2b00 (11008) and it's landing as _plt_save_size .
06:58:57 <danmcd> Node's large use of threads, memory management, etc. appear to put us into a situation where we don't have enough thread-stack to make that happen.
06:59:09 <danmcd> ld.so.1`_plt_save_size:         2b00             
06:59:21 <danmcd> THat's on Sapphire Rapids (AMX available...)
07:00:26 <danmcd> Alder Lake is smaller:
07:00:27 <danmcd> ld.so.1`_plt_save_size:         a88              
07:00:59 <danmcd> Ooops, not alder lake, that's Crystal Lake (11th Gen core)
07:01:35 <danmcd> Same on alder lake.
07:02:09 <danmcd> This explains my segv.
07:22:03 <danmcd> cpuid_get_xsave_size() returns MAX of our xsave_state structure size OR what the CPU reports
07:22:43 <danmcd> `cpuid_info0.cpi_xsave.xsav_max_size`   ==> this gets huge on AMX-equipped machines, and the block comment section about coping with AMX in the future lists the long set of problems.
07:23:25 <danmcd> We don't support AMX yet, so maybe just maybe we should make sure cpuid_get_xsave_size() is a bit more conservative?
07:25:25 <Woodstock> shouldn't it return MIN instead?
15:07:02 <danmcd> @Woodstock if we're making it static, possibly?  I'd like a 3rd opinion, and this coming week is Thanksgiving in the US so some of those opinion-holders may be travelling.
15:17:24 <danmcd> There's big commentary about coping with AMX in $UTS/intel/os/fpu.c. (99.99% sure it's a genuine rmustacc Epic Block Comment(TM).)
15:17:50 <Woodstock> danmcd: i haven't looked at the code in quite a while, it just seemed odd that we'd be using a value _larger_ than our structure
15:19:01 <danmcd> Intuitively it makes sense.  It was introduce in -gate with fenix illumos#8534 (and friends).
15:19:02 <fenix> FEATURE 8534: Want AVX-512 Support (Closed)
15:19:02 <fenix> ↳ https://www.illumos.org/issues/8534
15:20:37 <danmcd> I know getting MAX/MIN wrong is not uncommon, but IF it was gotten wrong, we had enough thread-stack-size to cope until AMX-machines showed up.
15:21:16 <danmcd> Also, it's quite possible the Node {,ab}usage we have in Triton might be doing things like creating threads with smaller stack sizes.
15:21:35 <danmcd> I'm gonna try a dirty hotpatch trick right now in my kernel...
15:39:57 <danmcd> Yeah it stopped the bleeding.
15:40:19 <danmcd> mdb -ke "cpuid_info0::print -athd cpi_xsave.xsav_max_size"  ==> How much is YOUR CPU reporting it needs at most for XSAVE
15:40:59 <danmcd> My reports above from _plt_save_size come right from the kernel's saved CPU state, which is set per-process at exec() time.
15:58:29 <danmcd> My hotpatch was to shrink Sapphire Rapids xsav_max_size to Alder Lake sizes (2696 vs. 11008).  The other possible hotpatch is to literally fix cpuid_get_xsave_size() to put MIN in instead of MAX.
15:58:47 <danmcd> (cmovq.ae becomes cmovq.be)
16:19:57 <danmcd> If @Woodstock is correct about cpuid_get_xsave_size() (s/MAX/MIN/), we should file a bug and fix this.  If he's not, we need to know why.
16:20:55 <danmcd> Pardon the paste:  A quick what-I-Can-see CPU survey (HDC is Zen2 so not included as there's a Zen2 already)
16:21:19 <danmcd> note, sizeof (struct xsave_state) == 832
16:21:23 <danmcd> VMware emulated kneecap ==> 832
16:21:23 <danmcd> Kebecloud nodes:  Xeon E[35] - Gen3 (Haswell/Haswell-E) ==> 832
16:21:23 <danmcd> mango: EPYC 7302P (Zen2) ==> 896
16:21:25 <danmcd> My big NUC: Core Gen11 Mobile (Tiger Lake) ==> 2696
16:21:27 <danmcd> My small NUC: N100 (Alder Lake) ==> 2696
16:21:29 <danmcd> Shiny new Box: Xeon Scalable Gen4 ==> 11008
17:24:54 <sommerfeld> danmcd: would not be surprised if MAX of what-hardware-reports and our struct size is intentional (on the theory that hardware may write up to N bytes so we need that much space reserved)
17:25:05 <sommerfeld> (if all bells and whistles are enabled, that is).
17:26:56 <sommerfeld> See https://www.illumos.org/issues/8534 
17:26:57 <fenix> → FEATURE 8534: Want AVX-512 Support (Closed)
17:27:22 <sommerfeld> or rather https://www.illumos.org/issues/8536
17:27:23 <fenix> → FEATURE 8536: xsave area should size dynamically, based on CPU features (Closed)
17:27:46 <sommerfeld> AVX512 adds almost 2k to the xsave area in each LWP. Intel clearly intends for the xsave area to be dynamically sized based on the features available in the current CPU. We should do that instead of blindly just increasing the size as we did for AVX.
17:27:57 <sommerfeld> (that was a quote from 8536)
18:55:09 <sommerfeld> (are their BIOS settings to disable AMX and does that shrink the reported max save size?)
22:51:10 <gitomat> [illumos-gate] 17748 installboot: potential null pointer dereference -- Toomas Soome <tsoome⊙mc>